The present invention generally concerns the surface treatment of semiconductor materials, and particularly treating the surface of substrates intended for the fabrication of components for microelectronic and/or optoelectronic applications. More precisely, the invention concerns a technique for enhancing the condition of the free surface of a semiconductor wafer, wherein the method includes a rapid thermal annealing step to smooth the free surface.
The term “free surface” means the surface of a wafer which is exposed to the outside environment (as compared with an interface surface which is in contact which the surface of another wafer or another element). The term “rapid thermal annealing” means rapid annealing in a controlled atmosphere, following a method that is conventionally known as the RTA method, which is the abbreviation for Rapid Thermal Annealing. In the remainder of this description, this method shall be called rapid thermal annealing or RTA.
RTA annealing of a wafer of material typically means that the wafer is annealed at a high temperature, which may be in the region of 1100° C. to 1300° C. for 1 to 60 seconds. RTA annealing is conducted in a controlled atmosphere. For example, the atmosphere may contain a mixture of hydrogen and argon, or an atmosphere of pure argon.
A method for producing a semiconductor wafer is the SMART-CUT® method. Its main steps include implanting atoms under a surface of a semiconductor substrate (silicon in particular) in an implantation zone of the substrate, bonding by close contact the implanted substrate with a stiffener, and detaching the implanted substrate at the implantation zone. Thus, that part of the substrate located between the surface submitted to implantation and the implantation zone is transferred onto the stiffener to form a thin film, or a layer, of semiconductor material upon the stiffener. Atomic implantation means any bombardment of atom or ion species capable of inserting these species into the wafer material with a maximum concentration of implanted species located at a predetermined depth of the wafer relative to the bombarded surface to define a weakened zone. The depth of the weakened zone depends upon the type of species implanted, and on their implanting energy.
The general term “wafer” may mean the film or layer that is transferred by using a method of the SMART-CUT® type. The semiconductor wafer may therefore be associated with a stiffener and optionally with other intermediate layers. The term “wafer” also covers any wafer, layer or film of semiconductor material such as silicon, whether or not the wafer has been produced by a method of the SMART-CUT® type.
For the applications mentioned above, the roughness specifications associated with the free surface of wafers are very stringent. The roughness of the free surface of wafers is a parameter which, to a certain extent, determines the quality of the components which are to be made on the wafer. It is therefore common to find roughness specifications which do not exceed 5 Angstroms in rms value (the abbreviation rms stands for “root mean square”).
Roughness measurements are generally made using an Atomic Force Microscope (“AFM”). This type of apparatus is used to measure roughness on surfaces by scanning a tip of the AFM microscope, and the measurement ranges from 1×1 μm2 to 10×10 μm2, and typically 50×50 μm2, and sometimes 100×100 μm2.
Roughness can be characterized according to two modalities. First, roughness is said to be high frequency and relates to scanned surfaces on the order of 1×1 μm2. Second, roughness is said to be low frequency and relates to scanned surfaces on the order of 10×10 μm2 or greater. The 5-Angstrom specification given above by way of example therefore corresponds to a roughness of a scanned surface of 10×10 μm2.
Wafers produced using known methods (such as SMART-CUT® or other methods) have surface roughness values which are greater than those mentioned above, unless the surface is subjected to a specific treatment such as polishing. A first known method for reducing the roughness of wafer surfaces consists of submitting the wafer to “conventional” heat treatment (sacrificial oxidation for example). But such treatment does not make it possible to reduce the wafer roughness to the level of the above-mentioned specifications. In order to further reduce roughness, it is possible to envisage increasing the number of conventional heat treatment steps and/or combining them with other known methods. But such techniques lead to a method that is lengthy and complex.
A second known method consists of subjecting the free surface of the wafer to chemical-mechanical polishing. This method can indeed reduce the roughness of the free surface of the wafer. However, if a defect concentration gradient that increases towards the free surface of the wafer exists, this second method can also abrade the wafer down to a zone that presents an acceptable concentration of defects. But this second known method can compromise the uniformity of the free surface of the wafer. This drawback is worsened when a large amount of polishing is performed on the surface of the wafer, as would be necessary to reach the roughness levels mentioned above.
A third method concerns subjecting the wafer to RTA annealing in a controlled atmosphere. This third method permits, in generally satisfactory manner, reduction of the surface roughness of wafers (in particular without deteriorating the thickness uniformity of the effective layer) and this therefore offers a solution of interest. However, while it is indeed possible to achieve globally satisfactory high frequency and low frequency roughness values with this third method, it has been observed that submitting the wafer to RTA annealing can lead to a disadvantage. In particular, on fine analysis of the surface condition of wafers (silicon wafers in particular) which have undergone such treatment, it has been found that holes of very small size were superimposed on a surface whose general roughness was otherwise satisfactory. Such analysis can be made by observation through an atomic force microscope. These small holes typically have a size on the order of a few nm in depth and a few dozen nm in diameter. These holes are similar to the holes that can sometimes be observed on the surface of materials such as silicon and which are attributed to a so-called ‘pitting’ phenomenon.
The term “pitting” will be used in this description for reasons of practicality, and it should be understood that the depth to diameter ratio of these small holes is less than the ratios usually encountered in conventional cases of pitting. More precisely, the “pitting” at issue herein does not have the same cause as the “pitting” phenomenon which is generally described in the state of the art. Pitting in the state of the art is generally due to defects embedded in the thickness of the wafer material. These defects may be attacked by heat treatment (for example heat treatment to improve the surface condition of the wafer). Therefore, in the state of the art, the phenomenon of pitting relates to holes generated by the attack of embedded defects. In this respect, reference may be made to PCT application WO01/28000 which specifies the characteristics of these embedded defects; in particular defects of the “COP” type, wherein COP stands for “Crystal Originated Particle”. Reference may be made for example to the passage on page 1 lines 48 to 54 of this patent application. It should also be noted that this application only sets out to improve the “long period” components of roughness, which relate to low frequency roughness (scanned surfaces in the order of 10×10 μm2) whereas high frequency components of roughness are not treated (see in particular page 10 lines 54-55 of this application). Yet the phenomenon designated as “pitting” in this description also relates to high frequency roughness.
In other documents, for example U.S. Pat. No. 6,372,609 or PCT application WO01/15215, the same treatment objective for conventional “pitting” is also described. Consequently, in these documents, the term “pitting” is not the same “pitting” which is addressed by the present invention.
For example U.S. Pat. No. 6,372,609 specifies that the targeted defects are of the “COP” type, which are embedded defects and the attack used is likely to generate fairly deep holes. U.S. Pat. No. 6,372,609 therefore specifies (see, for example, column 2, line 55 to column 3, line 24) that COPS may extend down to the embedded oxide layer of a structure of SOI type (that is to say that these defects may extend into the thickness of the material as far as the embedded oxide layer which is located underneath an effective layer of silicon whose thickness may typically reach a few thousand angstroms). The corresponding “pitting” holes, in the case of U.S. Pat. No. 6,372,609, therefore have a depth that may possibly reach these values of a few thousand angstroms. Therefore “pitting” as understood in the state of the art designates holes that are generated by the attack of defects embedded in the thickness of the wafer layer, wherein such holes may have a depth on the order of a few thousand angstroms. Conversely, the “pitting” of concern in the present application does not result from the attack of pre-existing defects, but only relates to places on the wafer surface on which reconstruction smoothing by RTA annealing is not fully achieved, causing the onset of the small holes mentioned above. The “pitting” at issue herein is therefore a purely superficial phenomenon.